IBM Research announced on June 25, 2026, the world's first sub-1nm semiconductor technology, a breakthrough that could extend Moore's Law by at least another decade. The 0.7nm Nanostack architecture vertically stacks transistors in a 3D "block of flats" design, achieving nearly double the transistor density of IBM's 2nm chip unveiled in 2021. This milestone arrives as the semiconductor industry approaches the physical limits of traditional 2D scaling.
What Happened
IBM unveiled its 0.7nm Nanostack chip technology at the Albany NanoTech Complex in New York, marking the first time any company has demonstrated functional transistors below the 1-nanometer barrier. The prototype chip integrates nearly 100 billion transistors on a surface area the size of a human fingernail — roughly twice the density of IBM's 2nm node announced in 2021. The Nanostack architecture uses a sequential 3D stacking approach where two transistors are vertically bonded together, each consisting of three nanosheet channels, creating what IBM describes as a "block of flats" design that builds upward rather than outward.
According to IBM Research, the sub-1nm platform delivers up to 70% higher energy efficiency or 50% greater performance compared to the 2nm node. The technology leverages High-NA EUV lithography and a novel dry resist process developed in collaboration with Lam Research, with test wafers already running since 2025. IBM projects a path to production in approximately five years, with first product tapeouts expected in late 2026 and production ramp through 2027. Senator Chuck Schumer hailed the breakthrough as proof that American semiconductor innovation still leads the world.
Why It Matters
The sub-1nm breakthrough addresses the semiconductor industry's most pressing challenge: the slowing of Moore's Law as traditional 2D scaling hits atomic-scale limits. By moving to 3D vertical stacking, IBM's Nanostack architecture opens a pathway for at least a decade of continued scaling — from 7 angstroms (0.7nm) down to 1 angstrom — potentially enabling chip generations far beyond what current roadmaps from TSMC, Samsung, and Intel project. For AI workloads, IBM estimates the technology could reduce frontier large language model training time from roughly three months to just two weeks, driven by a 40% SRAM scaling gain and the massive density improvement.
The geopolitical implications are significant. The breakthrough was achieved at the Albany NanoTech Complex, a New York state-funded research hub that anchors America's CHIPS Act ambitions. It demonstrates that U.S.-based research can still lead fundamental semiconductor innovation, even as high-volume manufacturing has largely shifted to Taiwan and South Korea. IBM's partnership with Japan's Rapidus for 2nm production and now sub-1nm development signals a coordinated allied approach to semiconductor sovereignty. For the global supply chain, the technology validates High-NA EUV and dry resist processes that will be essential for all future nodes, accelerating ecosystem readiness across the industry.
What's Next
IBM's immediate focus shifts from research demonstration to manufacturing readiness. The company plans to install High-NA EUV tools at Albany NanoTech for continued development, with the goal of achieving first product tapeouts by late 2026. Industry analysts note that while the lab breakthrough is remarkable, the five-year path to production faces hurdles in yield, thermal management for 3D-stacked structures, and the immense capital expenditure required for High-NA EUV volume manufacturing. Mukesh Khare, VP of Hybrid Cloud Research at IBM, stated the sub-1nm platform provides "at least a decade of future scaling" — but commercial adoption will depend on whether foundry partners like Intel Foundry Services or Rapidus can integrate Nanostack into their process roadmaps.
For the broader market, attention now turns to TSMC and Samsung's responses. Both companies have 1.4nm and 1nm nodes in development using different architectural approaches — TSMC with nanosheet transistors and Samsung with MBCFET (Multi-Bridge Channel FET). IBM's Nanostack represents a distinct 3D stacking path that could complement or compete with these roadmaps. The next key milestone will be the IEEE International Electron Devices Meeting (IEDM) in December 2026, where IBM is expected to present detailed process data and reliability metrics. Until then, the semiconductor ecosystem will be evaluating whether vertical 3D stacking becomes the universal paradigm for post-1nm scaling.
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Is a sub-1nm chip possible?
Yes, IBM has demonstrated the world's first functional sub-1nm chip using a 0.7nm Nanostack architecture. The prototype integrates nearly 100 billion transistors on a fingernail-sized die, proving that scaling below 1nm is technically achievable through 3D vertical stacking rather than traditional 2D shrinkage.
What is IBM's Nanostack architecture?
Nanostack is a sequential 3D stacking CMOS transistor architecture where two transistors are vertically bonded together. Each transistor consists of three nanosheet channels with flexible placement of top and bottom channels, creating a thermally stable structure that IBM describes as a "block of flats" design building upward rather than outward.
When will sub-1nm chips enter production?
IBM projects a path to production in approximately five years. Test wafers have been running since 2025, with first product tapeouts expected in late 2026 and production ramp through 2027 at the Albany NanoTech Complex using High-NA EUV lithography.
How does sub-1nm technology benefit AI computing?
IBM estimates the Nanostack architecture could reduce frontier large language model training time from roughly three months to just two weeks. The 70% energy efficiency gain and 40% SRAM scaling improvement directly address the power and performance bottlenecks in AI data centers.
How does IBM's sub-1nm compare to TSMC and Samsung roadmaps?
TSMC and Samsung are developing 1.4nm and 1nm nodes using nanosheet and MBCFET architectures respectively. IBM's 0.7nm Nanostack takes a different approach with 3D vertical stacking, potentially enabling scaling down to 1 angstrom — a full decade beyond current industry roadmaps.